? semiconductor components industries, llc, 2003 september, 2003 ? rev. 0 publication order number: ema6dxv5t1/d 1 ema6dxv5t1, EMA6DXV5T5 preferred devices dual common emitter bias resistor transistor pnp silicon surface mount transistors with monolithic bias resistor network this new series of digital transistors is designed to replace a single device and its external resistor bias network. the brt (bias resistor transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base?emitter resistor. the brt eliminates these individual components by integrating them into a single device. the use of a brt can reduce both system cost and board space. the device is housed in the sot?553 package which is designed for low power surface mount applications. ? simplifies circuit design ? reduces board space ? reduces component count ? moisture sensitivity level: 1 ? esd rating ? human body model: class 1 ? machine model: class b ? available in 7 inch tape and reel ? lead?free solder plating maximum ratings (t a = 25 c unless otherwise noted) rating symbol value unit collector-base voltage v cbo 50 vdc collector-emitter voltage v ceo 50 vdc collector current i c 100 madc thermal characteristics characteristic symbol max unit total device dissipation t a = 25 c derate above 25 c p d 230 (note 1) 338 (note 2) 1.8 (note 1) 2.7 (note 2) mw c/w thermal resistance ? junction-to-ambient r ja 540 (note 1) 370 (note 2) c/w thermal resistance ? junction-to-lead r jl 264 (note 1) 287 (note 2) c/w junction and storage temperature range t j , t stg ?55 to +150 c device marking and resistor values device marking r1 (k) r2 (k) ema6dxv5t1 ud 47 1. fr?4 @ minimum pad 2. fr?4 @ 1.0 x 1.0 inch pad ud m preferred devices are recommended choices for future use and best overall value. ud= specific device code m = date code pnp silicon bias resistor transistor http://onsemi.com r2 r1 marking diagram sot?553 case 463b 1 5 1 5 device package shipping ordering information ema6dxv5t1 sot?553 4 mm pitch 4000/tape & reel EMA6DXV5T5 sot?553 2 mm pitch 8000/tape & reel (3) (2) (1) (4) (5) / (6) ema6 / uma6n
ema6dxv5t1, EMA6DXV5T5 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics collector?base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector?emitter cutoff current (v ce = 50 v, i b = 0) i ceo ? ? 500 nadc emitter?base cutoff current (v eb = 6.0 v, i c = 0) i ebo ? ? 0.2 madc collector?base breakdown voltage (i c = 10 a, i e = 0) v (br)cbo 50 ? ? vdc collector?emitter breakdown voltage (note 3) (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc on characteristics (note 3) dc current gain (v ce = 10 v, i c = 5.0 ma) h fe 160 350 ? collector?emitter saturation voltage (i c = 10 ma, i b = 1.0 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 3.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.25 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor r1 32.9 47 61.1 k 3. pulse test: pulse width < 300 s, duty cycle < 2.0% figure 1. derating curve 350 200 150 100 50 0 ?50 0 50 100 150 t a , ambient temperature (5 c) p d, power dissipation (mw) r ja = 370 c/w 250 300
ema6dxv5t1, EMA6DXV5T5 http://onsemi.com 3 the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 150 milliwatts. information for using the sot?553 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. sot?553 power dissipation p d = t j(max) ? t a r ja p d = 150 c ? 25 c 833 c/w = 150 milliwatts the power dissipation of the sot?553 is a function of the pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet for the sot?553 package, p d can be calculated as follows: the 833 c/w for the sot?553 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milli- watts. there are other alternatives to achieving higher power dissipation from the sot?553 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. there- fore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device. sot?553 1.35 0.0531 0.5 0.0197 mm inches 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118
ema6dxv5t1, EMA6DXV5T5 http://onsemi.com 4 package dimensions sot?553 xv5 suffix 5?lead package case 463b?01 issue o g m 0.08 (0.003) x d 5 pl c j ?x? ?y? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. dim a min max min max inches 1.50 1.70 0.059 0.067 millimeters b 1.10 1.30 0.043 0.051 c 0.50 0.60 0.020 0.024 d 0.17 0.27 0.007 0.011 g 0.50 bsc 0.020 bsc j 0.08 0.18 0.003 0.007 k s a b y 12 3 4 5 s k 0.004 0.012 0.059 0.067 0.10 0.30 1.50 1.70 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ema6dxv5t1/d thermal clad is a trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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